The current paths in electronic assemblies that include processors are continually being required to handle ever-increasing amounts of I/O signals. Processors typically require additional I/O signals in order to address the ever-increasing functionality of new applications.
Power and I/O signals are typically delivered to the processor through a substrate using a socket (e.g., a land grid array) that is situated underneath the substrate where the processor is mounted. There is a strong incentive to increase the contact density of the sockets in order to provide additional I/O signals to the processor (among other reasons).
A typical land grid array (LGA) on a socket may include over 1000 contacts and often requires a compression load in order to adequately engage the contacts on the socket with pads on a substrate. The contacts in existing LGA's are typically arranged so that there is capacitive and inductive coupling between adjacent contacts. These adjacent contacts form a differential contact pair.
One drawback with reducing contact pitch in order to increase contact density is that the capacitive coupling increases between the contacts which are in adjacent differential contact pairs. The increased capacitive coupling between the contacts in adjacent differential contact pairs reduces the differential characteristic impedance of the contact pair according to the relationship Zo=(L/C)1/2 (where L=the distributed inductance of the contact pair and C=the distributed capacitance).
When the differential characteristic impedance of a contact pair drops below an optimum value, the capacitive coupling between the contacts in adjacent differential contact pairs can negatively affect the high speed performance of a reduced-pitch socket. The optimum value of the differential characteristic impedance for each differential contact pair would be a value that matches the overall system differential impedance.
There is a need for a reduced pitch socket assembly where the arrangement of the contacts in the socket assembly minimizes capacitive coupling between the contacts that are in adjacent differential contact pairs. In addition, the socket assembly should minimize socket performance degradation as the data rate within electronic assemblies increases to greater than 20 Gb/s.